The present invention relates to a method for forming an integrated circuit polysilicon resistor in a high performance CMOS process.
Mixed signal integrated circuits often require resistors for proper circuit operation. Typically such resistors are formed using doped polycrystalline silicon. Metal oxide semiconductor (MOS) transistors, which are also present on the mixed signal integrated circuits, have a gate electrode that also comprises polycrystalline silicon. To lower the resistances present in the MOS transistor a metal silicide layer is formed on the polysilicon gate electrode of the MOS transistor. Metal silicide layers are also formed on the source and drain regions of the MOS transistor. In order for the integrated circuit resistors to have the desired resistance values in the limited space available it is important that no metal silicide be formed on the surface of the resistors. In addition to the resistance value it is important that the resistors exhibit a low thermal coefficient of resistance allowing proper circuit operation over a wide range of temperature values. The integrated circuit resistor thermal coefficient of resistance depends on the doping concentration and it is important that the polysilicon resistor be formed using the proper dopant concentration. Using current integrated circuit manufacturing methods, the integration of polysilicon resistors with the above properties often requires the addition of expensive processing steps that have a deleterious effect on the performance of the MOS transistors. There is therefore a need for a method to form integrated circuit resistors with the above described properties without adding expensive steps to existing manufacturing processes. The instant invention addresses this need and presents a method for forming an integrated circuit polysilicon resistor in a high performance complementary metal oxide semiconductor (CMOS) process.
The instant invention describes a method for forming an integrated circuit resistor. In particular the method comprises forming an insulator region in a semiconductor. A dielectric layer is then formed on the insulator and polysilicon layers are simultaneously formed on the dielectric layer and the insulator layer. The polysilicon layer formed on the dielectric layer will function as the MOS transistor gate structure and the polysilicon layer formed on the dielectric layer will function as the polysilicon resistor. Silicon nitride spacer structures adjacent said second polysilicon layer and a patterned silicon nitride layer over the upper surface of the first polysilicon layer are then simultaneously formed. Both polysilicon layers are implanted either during the formation of either the p-type source drain regions of the PMOS transistors or the n-type source drain regions of the NMOS transistors. A metal silicide is then formed on the surface of the resistor polysilicon layer not covered by the patterned silicon nitride layer.